写在前边：本片著述基于DP1.4法度的draft版块蝴蝶谷网站，关联词和最终版块依然莫得太大永逝。

追溯了Main-Link， AUX， HPD， SST， MST， Training Syntax and Sequence等伏击特点。

DP传输信号的关节部分

从Source到Device的传输，主要由主链路，AUX通谈和HPD组成。

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图片蝴蝶谷网站

DP Main-Link 主链路

单向，1条或2条或4条 AC耦合的、双端差分高速信号链路

链路传输速度(Link rate):  1.62Gbps， 2.7Gbps， 5.4Gbps， 8.1Gbps/lane. 淌若是多条链路同期传输，那么通盘通谈必须责任在合并个link rate。带宽如下：

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莫得单独的时钟链路。

编码神志：8b/10b编码。易于纠错且利于DC平衡。

Pixel Data Mapping的例子: 

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AUX 通谈

AC耦合，双端（50欧姆端接电阻），差分信号

双向，半双工，通过AUX通谈的通信不错竣事链路惩处和开辟鸿沟

主(Master)：DP Source

从(Slave)：DP Sink

传输神志：1Mbps曼彻斯特编码。淌若撑抓Fast AUX transaction， 那么不错到720Mbps

基本原则（语法）：AUX transaction老是由Upstream发起。 Source和Sink不错通过Native AUX大略I2C over AUX大略USB over AUX的神志通信。淌若通过USB over AUX通信，那么需要撑抓Fast AUX。

硬件设想规矩：

The upstream DP device must weakly pull down the AUX+ line to GND and weakly pull up the AUX- line to DP_PWR each with a resistor in the range 10kΩ to 105kΩ between the AC-coupling capacitor and the upstream device connector to assist detection of the upstream DP device and powered upstream DP device by the downstream device. A nominal 100kΩ resistor valueis recommended.（Source和Sink两头对AUX有上拉和下拉，诈欺中汽主要见解是保管驱动智商）All downstream devices must have AC-coupling capacitors， regardless of whether they implement upstream DP device detection. The downstream devices must very weakly pull up AUX+ line and very weakly pull down AUX- line with 1MΩ (±5%) resistors between the downstream device connector and the AC-coupling capacitors. When AUX+ line DC voltage is L level， it means an upstream DP device is connected. When AUX- line DC voltage is H level， it means that a powered upstream DP device is connected.（耦合电容对AUX通谈也特殊伏击，一般是0.1uF）

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HPD

HPD是由DP Sink发起的单向中断信号

有三种HPD scenario：

Case1: DP sink接入，Sink端拉低HPD电平发起HPD中断。HPD脉冲宽度在0.25ms~2ms之间。DPTX需要再IRQ_HPD_Pulse高潮沿后的100ms以内读DPRX DPCD的开辟景色。2ms是HPD脉冲的超平素间。

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Case2: DP sink断开流畅。当HPD脉冲的低电平抓续技术起头2ms，DPTX会恭候HPD电平被重新拉高。

Case3: Hot Plug/Re-plug. DPTX也要读DPCD。

HPD信号检测法度:

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HPD de-bounce time:

- DPTX are recommended to implement de-bouncing of the HPD signal on an external connection- A period of 100 ms is recommended for the detection of an HPD connect event.比如 the event， “HPD High”， is confirmed only after HPD has been asserted continuously for 100 ms.

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SST形式

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Main-Link: 传输蝴蝶谷网站

Link and device management over AUX：发现，成就和钦慕Link流畅。AUX探询DPCD等于这个见解。

Link Layer: Provides services as instructed or requested by the Stream/Link Policy makers

Source 和 Sink devices皆必须有底下两个policy makers：

Stream Policy Maker: manages the transport of the stream

Link Policy Maker: manages the link and is responsible for keeping the link synchronized.

Lanes data rate修复：DPRX必须通过DPCD寄存器形色其接受智商。DPTX在读取DPRX DPCD后，必须成就DPCD Link FiledConfiguration reg. 然后脱手link training。Mainlink通谈的信号传输相识性和 PCB设想， DP 线， DP connector皆关考虑。

SST同步传输做事：

数据mapping：Packing/Unpacking，Stuffing/Unstuffing，Framing/Unframing，Inter-lane skewing/de-skewing

Stream CLK regeneration

Main stream attribute data insertion

Secondary-Data Packet(SDP) optional insertion

AUX通谈

AUX通谈的契约雷同最初是由DP Source发起的

Diagram of DPTX: 超平素间400us

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Diagram of DPRX: 超平素间300us

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判决：

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AUX 通谈做事

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数据流传输启动化轨则

1） Stream Policy maker在启动化传输之前需要先作念底下的事情：

读Sink的EDID；成立Main stream属性数据和CEA861 INFOFRAME

从Link Policy Maker得到数据：RX接受智商（Number and types of ports available in RX）；Link configuration(Total link bandwidth); Link status(Synchronized? Excessive error symbols?)

2) When a stream is ready for transport， the Stream Policy Maker must start the transport of isochronous stream along withstream attributes data.

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Link Training:

DPTX检测到正确的HPD事件后，Link Policy Maker启动化Link Training

包括三种Training情况：Full Link training; Fast Link training; No link training

Link training的关节筹备： CR和EQ

Clock Recovery (CR)： Link training begins with the Clock Recovery (CR) sequence. 时钟锁定和差分电压Vpp成立. Locks the receiver CR (clock recovery) PLL when successful.

Channel Equalization (EQ)：Symbol-Lock & Inter-lane Alignment and Pre-emphasis setting. 

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夺目： Training发生在读RX DPCD，EDID之后。

Link training for DPCD：

CR time out: 100us

EQ time out: Optional. 400us， 4ms， 8ms， 12ms，16ms

在Fast training中，莫得AUX transaction

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CR：

通盘Devices必须撑抓TPS1和TPS2。 撑抓HBR2的Device还必须撑抓TPS3。撑抓HBR3的Device必须撑抓TPS4

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CR建立经过：

The receiver may defer setting LANEx_CR_DINE bits until the optimization is completed

If the receiver keeps the same value in ADJUST_REQUEST_LANEx_x， increase the voltage swing and/or pre-emphasis level according to the request

Unless all the LANEx_CR_DONE bit are set， the transmitter must read the ADJUST_REQUEST_LANEx_x， increease the and/or pre-emphasis level according to the request voltage swing

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EQ建立经过：

The Receiver(Downstream) must use the recognition of this training pattern to decide whether the channel equalization is successful or not.

允许的Vdiff_pp和PEQ 组合

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Training何时扫尾？

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SDP

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Pin assignment:

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Connection

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附录

DPCD地址

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